The present invention relates generally to integrated circuit memory devices and, more particularly, to a random access memory system of destructive-read memory cached by destructive-read memory.
The evolution of sub-micron CMOS technology has resulted in significant improvement in microprocessor speeds. Quadrupling roughly every three years, microprocessor speeds have now exceeded 1 Ghz. Along with these advances in microprocessor technology have come more advanced software and multimedia applications, which in turn require larger memories for the application thereof. Accordingly, there is an increasing demand for larger Dynamic Random Access Memories (DRAMs) with higher density and performance.
DRAM architectures have evolved over the years, being driven by system requirements that necessitate larger memory capacity. However, the speed of a DRAM, characterized by its random access time (tRAC) and its random access cycle time (tRC), has not improved in a similar fashion. As a result, there is a widening speed gap between the DRAMs and the CPU, since the clock speed of the CPU steadily improves over time.
The random access cycle time (tRC) of a DRAM array is generally determined by the array time constant, which represents the amount of time to complete all of the random access operations. Such operations include wordline activation, signal development on the bitlines, bitline sensing, signal write back, wordline deactivation and bitline precharging. Because these operations are performed sequentially in a conventional DRAM architecture, increasing the transfer speed (or bandwidth) of the DRAM becomes problematic.
One way to improve the row access cycle time of a DRAM system for certain applications is to implement a destructive read of the data stored in the DRAM cells, and then temporarily store the destructively read data into a buffer cell connected to the sense amplifier of the same local memory array. (See, for example, U.S. Pat. Nos. 6,205,076 and 6,333,883 to Wakayama, et al.) In this approach, different wordlines in a local memory array connected to a common sense amplifier block can be destructively read sequentially for a number of times, which is set by one plus the number of the buffer cells per sense amplifier. However, the number of buffer cells that can be practically implemented in this approach is small, due to the large area required for both the buffer cells and associated control logic for each local DRAM array. Furthermore, so long as the number of buffer cells is less than the number of wordlines in the original cell arrays, this system only improves access cycle time for a limited number of data access cases, rather than the random access cycle time required in general applications.
A more practical way to improve the random access cycle time of a DRAM system is to implement a destructive read of the data stored in the DRAM cells, and then temporarily store the destructively read data into an SRAM based cache outside of the main memory array. The SRAM based cache has at least the same number of wordlines as one, single-bank DRAM array. (The term “bank” as described herein refers to an array of memory cells sharing the same sense amplifiers.) This technique is described in U.S. patent application Ser. No. 09/843,504, entitled “A Destructive Read Architecture for Dynamic Random Access Memories”, filed Apr. 26, 2001, and commonly assigned to the assignee of the present application. In this technique, a delayed write back operation is then scheduled for restoring the data to the appropriate DRAM memory location at a later time. The scheduling of the delayed write back operation depends upon the availability of space within the SRAM based cache. While such an approach is effective in reducing random access cycle time, the use of an SRAM based cache may occupy an undesired amount of chip real estate, as well as result in more complex interconnect wiring to transfer data between the DRAM and the cache. Where chip area is of particular concern, therefore, it becomes desirable to reduce random access cycle time without occupying a relatively large device area by using an SRAM based cache.